vishay siliconix si4330dy document number: 72184 s09-0392-rev. d, 09-mar-09 www.vishay.com 1 dual n-channel 30-v (d-s) mosfet features ? halogen-free according to iec 61249-2-21 available ? trenchfet ? power mosfet ? 100 % r g tested applications ? notebook - load switch - dc/dc conversion - auxiliary voltage product summary v ds (v) r ds(on) ( )i d (a) 30 0.0165 at v gs = 10 v 8.7 0.022 at v gs = 4.5 v 7.5 s 1 d 1 g 1 d 1 s 2 d 2 g 2 d 2 so-8 5 6 7 8 t op v iew 2 3 4 1 ordering information: SI4330DY-T1-E3 (lead (pb)-free) si4330dy-t1-ge3 (lead (pb)-free and halogen-free) n-channel mosfet d 1 g 1 s 1 n-channel mosfe t d 2 g 2 s 2 notes: a. surface mounted on 1" x 1" fr4 board. absolute maximum ratings t a = 25 c, unless otherwise noted parameter symbol 10 s steady state unit drain-source voltage v ds 30 v gate-source voltage v gs 20 continuous drain current (t j = 150 c) a t a = 25 c i d 8.7 6.6 a t a = 70 c 7.0 5.3 pulsed drain current i dm 30 continuous source current (diode conduction) a i s 1.7 0.9 maximum power dissipation a t a = 25 c p d 2.0 1.1 w t a = 70 c 1.3 0.7 operating junction and storage temperature range t j , t stg - 55 to 150 c thermal resistance ratings parameter symbol typical maximum unit maximum junction-to-ambient a t 10 s r thja 45 62.5 c/w steady state 85 110 maximum junction-to-foot (drain) steady state r thjf 26 35
www.vishay.com 2 document number: 72184 s09-0392-rev. d, 09-mar-09 vishay siliconix si4330dy notes: a. pulse test; pulse width 300 s, duty cycle 2 %. b. guaranteed by design, not s ubject to production testing. stresses beyond those listed under ?absolute maximum ratings? ma y cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other condit ions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. typical characteristics 25 c, unless otherwise noted specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 13v gate-body leakage i gss v ds = 0 v, v gs = 20 v 100 na zero gate voltage drain current i dss v ds = 30 v, v gs = 0 v 1 a v ds = 30 v, v gs = 0 v, t j = 55 c 5 on-state drain current a i d(on) v ds 5 v, v gs = 10 v 30 a drain-source on-state resistance a r ds(on) v gs = 10 v, i d = 8.7 a 0.013 0.0165 v gs = 4.5 v, i d = 7.5 a 0.018 0.022 forward transconductance a g fs v ds = 15 v, i d = 8.7 a 28 s diode forward voltage a v sd i s = 1.7 a, v gs = 0 v 0.8 1.2 v dynamic b total gate charge q g v ds = 15 v, v gs = 4.5 v, i d = 8.7 a 13 20 nc gate-source charge q gs 7.1 gate-drain charge q gd 3.5 gate resistance r g 0.5 1 1.7 tu r n - o n d e l ay t i m e t d(on) v dd = 15 v, r l = 15 i d ? 1 a, v gen = 10 v, r g = 6 10 15 ns rise time t r 10 15 turn-off delay time t d(off) 40 60 fall time t f 12 20 source-drain reverse recovery time t rr i f = 1.7 a, di/dt = 100 a/s 45 70 output characteristics 0 6 12 18 24 30 0.0 0.5 1.0 1.5 2.0 2.5 3. 0 v gs = 10 thru 5 v 3 v v ds - drain-to-source voltage (v) - drain current (a) i d 4 v transfer characteristics 0 6 12 18 24 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 t c = 125 c - 55 c 25 c v gs - gate-to-source voltage (v) - drain current (a) i d
document number: 72184 s09-0392-rev. d, 09-mar-09 www.vishay.com 3 vishay siliconix si4330dy typical characteristics 25 c, unless otherwise noted on-resistance vs. drain current gate charge source-drain diode forward voltage - on-resistance ( r ds(on) ) 0.00 0.01 0.02 0.03 0.04 0 6 12 18 24 30 i d - drain current (a) v gs = 10 v v gs = 4.5 v 0 2 4 6 8 10 0 5 10 15 20 25 30 v ds = 15 v i d = 8.7 a - gate-to-source voltage (v) q g - total gate charge (nc) v gs 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 t j = 150 c 30 10 1 v sd - source-to-drain voltage (v) - source current (a) i s t j = 25 c capacitance on-resistance vs. junction temperature on-resistance vs. gate-to-source voltage 0 600 1200 1800 2400 0 6 12 18 24 30 v ds - drain-to-source voltage (v) c oss c iss c - capacitance (pf) c rss 0.6 0.8 1.0 1.2 1.4 1.6 - 50 - 25 0 2 5 5 0 7 5 100 125 150 v gs = 10 v i d = 8.7 a t j - junction t e mperature (c) (normalized) - on-resistance r ds(on) 0.00 0.02 0.04 0.06 0.08 0.10 0246810 i d = 8.7 a - on-resistance ( r ds(on) ) v gs - gate-to-source voltage (v)
www.vishay.com 4 document number: 72184 s09-0392-rev. d, 09-mar-09 vishay siliconix si4330dy typical characteristics 25 c, unless otherwise noted threshold voltage - 1.0 - 0.8 - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 - 50 - 25 0 25 50 75 100 125 150 i d = 250 a variance (v) v gs(th) t j - temperature (c) single pulse power 0 30 50 10 20 power (w) time (s) 40 1 100 600 10 10 - 1 10 - 2 safe operating area 100 1 0.1 1 10 100 0.01 10 t a = 25 c single pulse p(t) = 10 dc 0.1 i d( on) limited ds(on) * limited by r bvdss limited p(t) = 1 p(t) = 0.1 p(t) = 0.01 p(t) = 0.001 i dm limited v ds - drain-to-source voltage (v) *v gs > minimum v gs at which r ds(on) is specified - drain current (a) i d normalized thermal transient im pedance, junction-to-ambient 10 - 3 10 - 2 1 1 0 600 10 - 1 10 - 4 100 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square w ave pulse duration (s) normalized ef fective t ransient thermal impedance 1. duty cycle, d = 2. per unit base = r th j a = 85 c/w 3. t jm - t a = p dm z th j a (t ) t 1 t 2 t 1 t 2 notes: 4. surface mounted p dm
document number: 72184 s09-0392-rev. d, 09-mar-09 www.vishay.com 5 vishay siliconix si4330dy typical characteristics 25 c, unless otherwise noted vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72184 . normalized thermal transient impedance, junction-to-foot 10 - 3 10 - 2 110 10 - 1 10 - 4 2 1 0.1 0.01 0.2 0.1 0.05 0.02 single pulse duty cycle = 0.5 square wave pulse duration (s) normalized eff ective transient thermal impedance
vishay siliconix package information document number: 71192 11-sep-06 www.vishay.com 1 dim millimeters inches min max min max a 1.35 1.75 0.053 0.069 a 1 0.10 0.20 0.004 0.008 b 0.35 0.51 0.014 0.020 c 0.19 0.25 0.0075 0.010 d 4.80 5.00 0.189 0.196 e 3.80 4.00 0.150 0.157 e 1.27 bsc 0.050 bsc h 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 l 0.50 0.93 0.020 0.037 q0808 s 0.44 0.64 0.018 0.026 ecn: c-06527-rev. i, 11-sep-06 dwg: 5498 4 3 1 2 5 6 8 7 h e h x 45 c all le a d s q 0.101 mm 0.004" l ba 1 a e d 0.25 mm (g a ge pl a ne) s oic (narrow): 8-lead jedec p a rt n u m b er: m s -012 s
vishay siliconix trenchfet ? power mosfets application note 808 mounting little foot ? , so-8 power mosfets application note document number: 70740 www.vishay.com revision: 18-jun-07 1 wharton mcdaniel surface-mounted little foot power mosfets use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. leadframe materials and design, molding compounds, and die attach materials have been changed, while the footpr int of the packages remains the same. see application note 826, recommended minimum pad patterns with outline drawin g access for vishay siliconix mosfets, ( http://www.vishay.com/ppg?72286 ), for the basis of the pad design for a little foot so-8 power mosfet. in converting this recommended minimum pad to the pad set for a power mosfet, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. in the case of the so-8 p ackage, the thermal connections are very simple. pins 5, 6, 7, and 8 are the drain of the mosfet for a single mosfet package and are connected together. in a dual package, pi ns 5 and 6 are one drain, and pins 7 and 8 are the other drain. for a small-signal device or integrated circuit, typical co nnections would be made with traces that are 0.020 inches wi de. since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. the total cross section of the copp er may be adequate to carry the current required for the a pplication, but it presents a large thermal impedance. also , heat spreads in a circular fashion from the heat source. in this case the drain pins are the heat sources wh en looking at heat spread on the pc board. figure 1. single mosfet so-8 pad pattern with copper spreading figure 2. dual mosfet so-8 pad pattern with copper spreading the minimum recommended pad patterns for the single-mosfet so-8 with copp er spreading (figure 1) and dual-mosfet so-8 with copper spreading (figure 2) show the starting point for utilizing th e board area available for the heat-spreading copper. to creat e this pattern, a plane of copper overlies the drain pins . the copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat fr om the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. these patterns use all the available area underneath the body for this purpose. since surface-mounted packag es are small, and reflow soldering is the most comm on way in which these are affixed to the pc board, ?t hermal? connections from the planar copper to the pads have not been used. even if additional planar copper area is used, there should be no problems in the soldering process. the actual solder connections are defined by the solder mask openings. by combining the basic footprint wi th the copper plane on the drain pins, the solder mask ge neration occurs automatically. a final item to keep in mind is the width of the power traces. the absolute minimum pow er trace width must be determined by the amount of current it has to carry. for thermal reasons, this minimum width should be at least 0.020 inches. the use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.196 5.0 0.2 88 7.3 0.050 1.27 0.027 0.69 0.07 8 1.9 8 0.2 5.07 0.0 88 2.25 0.2 88 7.3 0.050 1.27 0.0 88 2.25
application note 826 vishay siliconix www.vishay.com document number: 72606 22 revision: 21-jan-08 application note recommended minimum pads for so-8 0.246 (6.248) recommended mi nimum pads dimensions in inches/(mm) 0.172 (4.369) 0.152 (3.861) 0.047 (1.194) 0.028 (0.711) 0.050 (1.270) 0.022 (0.559) return to index return to index
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